library verilog;
use verilog.vl_types.all;
entity cmsdk_ahb_to_apb is
    generic(
        ADDRWIDTH       : integer := 16;
        REGISTER_RDATA  : integer := 1;
        REGISTER_WDATA  : integer := 0
    );
    port(
        HCLK            : in     vl_logic;
        HRESETn         : in     vl_logic;
        PCLKEN          : in     vl_logic;
        HSEL            : in     vl_logic;
        HADDR           : in     vl_logic_vector;
        HTRANS          : in     vl_logic_vector(1 downto 0);
        HSIZE           : in     vl_logic_vector(2 downto 0);
        HPROT           : in     vl_logic_vector(3 downto 0);
        HWRITE          : in     vl_logic;
        HREADY          : in     vl_logic;
        HWDATA          : in     vl_logic_vector(31 downto 0);
        HREADYOUT       : out    vl_logic;
        HRDATA          : out    vl_logic_vector(31 downto 0);
        HRESP           : out    vl_logic;
        PADDR           : out    vl_logic_vector;
        PENABLE         : out    vl_logic;
        PWRITE          : out    vl_logic;
        PSTRB           : out    vl_logic_vector(3 downto 0);
        PPROT           : out    vl_logic_vector(2 downto 0);
        PWDATA          : out    vl_logic_vector(31 downto 0);
        PSEL            : out    vl_logic;
        APBACTIVE       : out    vl_logic;
        PRDATA          : in     vl_logic_vector(31 downto 0);
        PREADY          : in     vl_logic;
        PSLVERR         : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of ADDRWIDTH : constant is 1;
    attribute mti_svvh_generic_type of REGISTER_RDATA : constant is 1;
    attribute mti_svvh_generic_type of REGISTER_WDATA : constant is 1;
end cmsdk_ahb_to_apb;
